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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The MC574HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4046A phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op-amp DEM OUT. The comparators have two common signal inputs, COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1 OUT and maintains 90 degrees phase shift at the center frequency between SIG IN and COMP IN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) provides digital error signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift between SIG IN and COMP IN signals (duty cycle is immaterial). The linear VCO produces an output signal VCO OUT whose frequency is determined by the voltage of input VCO IN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM OUT with an external resistor is used where the VCO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. * * * * * * * * * * Output Drive Capability: 10 LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 A Maximum (except SIGIN and COMPIN) In Compliance with the Requirements Defined by JEDEC Standard No. 7A Low Quiescent Current: 80 A Maximum (VCO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 70 Equivalent Gates
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC Name and Function Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0 V) VSS VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage
MC74HC4046A
N SUFFIX PLASTIC PACKAGE CASE 648-08
1
16
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
ORDERING INFORMATION MC74HCXXXXAN MC74HCXXXXAD Plastic SOIC
PIN ASSIGNMENT
PCPout PC1out COMPin VCOout INH C1A C1B GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC PC3out SIGin PC2out R2 R1 DEMout VCOin
10/95
(c) Motorola, Inc. 1995
3-1
REV 6
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MC74HC4046A
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW Tstg TL - 65 to + 150 260
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP and SOIC Package
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 3.0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) VCC DC Supply Voltage (Referenced to GND) NON-VCO 2.0 0 6.0 V Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Pin 5) VCC V - 55 0 0 0 + 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit 85C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 125C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 (continued) Unit V
Symbol VIH
Parameter Minimum High-Level Input Voltage DC Coupled SIGIN, COMPIN Maximum Low-Level Input Voltage DC Coupled SIGIN, COMPIN Minimum High-Level Output Voltage PCPOUT, PCnOUT
Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA
VCC Volts 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0
- 55 to 25_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48
VIL
V
VOH
V
MOTOROLA
3-2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS - continued (Voltages Referenced to GND)
Guaranteed Limit Symbol VOL Parameter Maximum Low-Level Output Voltage Qa-Qh PCPOUT, PCnOUT Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Iin Maximum Input Leakage Current SIGIN, COMPIN Vin = VCC or GND VCC Volts 2.0 4.5 6.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1 0.26 0.26 3.0 7.0 18.0 30.0 0.5 85C 0.1 0.1 0.1 0.33 0.33 4.0 9.0 23.0 38.0 5.0 125C 0.1 0.1 0.1 0.4 0.4 5.0 11.0 27.0 45.0 10 A Unit V
IOZ
Maximum Three-State Leakage Current PC2OUT Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3, 5 and 14 at VCC Pin 9 at GND; Input Leakage at Pins 3 and 14 to be excluded
Output in High-Impedance State Vin = VIH or VIL Vout = VCC or GND Vin = VCC or GND |Iout| = 0 A
A
ICC
6.0
4.0
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
[Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tTLH, tTHL Parameter Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 1) Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 1) Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT (Figure 1) Maximum Propagation Delay, SIGIN/COMPIN Output Disable Time to PC2OUT (Figures 2 and 3) Maximum Propagation Delay, SIGIN/COMPIN Output Enable Time to PC2OUT (Figures 2 and 3) Maximum Output Transition Time (Figure 1) VCC Volts 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit - 55 to 25_C 175 35 30 340 68 58 270 54 46 200 40 34 230 46 39 75 15 13 85C 220 44 37 425 85 72 340 68 58 250 50 43 290 58 49 95 19 16 125C 265 53 45 510 102 87 405 81 69 300 60 51 345 69 59 110 22 19 Unit ns
ns
ns
ns
ns
ns
High-Speed CMOS Logic Data DL129 -- Rev 6
3-3
MOTOROLA
MC74HC4046A
[VCO Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage INH Maximum Low-Level Input Voltage INH Minimum High-Level Output Voltage VCOOUT Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA VOL Maximum Low-Level Output Voltage VCOOUT Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Iin Maximum Input Leakage Current INH, VCOIN Vin = VCC or GND VCC Volts 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 4.5 6.0 3.0 4.5 6.0 4.5 6.0 6.0 - 55 to 25_C 2.1 3.15 4.2 0.90 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 85C 2.1 3.15 4.2 0.9 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 125C 2.1 3.15 4.2 0.9 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 A V Unit V
VIL
V
VOH
V
Min VVCOIN Operating Voltage Range at VCOIN over the range specified for R1; For linearity see Fig. 15A, Parallel value of R1 and R2 should be > 2.7 k R1 Resistor Range INH = VIL 3.0 4.5 6.0 0.1 0.1 0.1
Max 1.0 2.5 4.0
Min 0.1 0.1 0.1
Max 1.0 2.5 4.0
Min 0.1 0.1 0.1
Max 1.0 2.5 4.0 V
3.0 4.5 6.0 3.0 4.5 6.0
3.0 3.0 3.0 3.0 3.0 3.0 40 40 40
300 300 300 300 300 300 No Limit
3.0 3.0 3.0 3.0 3.0 3.0
300 300 300 300 300 300
3.0 3.0 3.0 3.0 3.0 3.0
300 300 300 300 300 300
k
R2
C1
Capacitor Range
3.0 4.5 6.0
pF
MOTOROLA
3-4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
[VCO Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit VCC Volts 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3 11 13 See Figures 15A, B, C - 55 to 25_C Min Max 85C Min Max 125C Min Max Unit %/K
Symbol f/T Frequency Stability with Temperature Changes (Figure 13A, B, C) VCO Center Frequency (Duty Factor = 50%) (Figure 14A, B, C, D) VCO Frequency Linearity
Parameter
fo
MHz
fVCO
%
VCO
Duty Factor at VCOOUT
Typical 50%
%
[Demodulator Section] DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit VCC Volts 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 - 55 to 25_C Min 50 50 50 Max 300 300 300 See Figure 12 85C Min Max 125C Min Max Unit k
Symbol RS
Parameter Resistor Range
Test Conditions At RS > 300 k the Leakage Current can Influence VDEMOUT Vi = VVCOIN = 1/2 VCC; Values taken over RS Range. VDEMOUT = 1/2 VCC
VOFF
Offset Voltage VCOIN to VDEMOUT Dynamic Output Resistance at DEMOUT
mV
RD
Typical 25
High-Speed CMOS Logic Data DL129 -- Rev 6
3-5
MOTOROLA
MC74HC4046A
SWITCHING WAVEFORMS
SIGIN, COMPIN INPUTS
VCC 50% GND tPHL tPLH 90% 50% 10% tTLH
SIGIN INPUT
VCC 50% GND VCC
COMPIN INPUT tPZH PC2OUT OUTPUT 50%
50% tPHZ 90% GND VOH HIGH IMPEDANCE
PCPOUT, PC1OUT PC3OUT OUTPUTS tTHL
Figure 1.
Figure 2.
VCC SIGIN INPUT 50% GND OUTPUT VCC COMPIN INPUT 50% tPZL PC2OUT OUTPUT 50% 10% tPLZ GND HIGH IMPEDANCE *INCLUDES ALL PROBE AND JIG CAPACITANCE VOL DEVICE UNDER TEST CL* TEST POINT
Figure 3.
Figure 4. Test Circuit
MOTOROLA
3-6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
DETAILED CIRCUIT DESCRIPTION
Voltage Controlled Oscillator/Demodulator Output The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1 are selected to determine the center frequency of the VCO (see typical performance curves Figure 14). R2 can be used to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the VCO range is from 0 Hz. The effect of R2 is shown in Figure 24, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for a narrow lock range, large swings on the VCO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 5. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges up to Vref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to VCO output (Pin 4). The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input accessible without degrading the loop performance, the VCO input voltage is buffered through a unity gain Op-amp to Demod Output. This Op-amp can drive loads of 50K ohms or more and provides no loading effects to the VCO input voltage (see Figure 12). An inhibit input is provided to allow disabling of the VCO and all Op-amps (see Figure 5). This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and all Op-amps, minimizing standby power consumption.
VREF 12 R2
+ _
I1 CURRENT MIRROR I1 + I2 = I3
VCOIN
9 11 R1
+ _
I2 I3
4
VCOOUT
DEMODOUT 10
+ _
C1 (EXTERNAL) 6 7
Vref + +
-
INH
5
Figure 5. Logic Diagram for VCO
High-Speed CMOS Logic Data DL129 -- Rev 6
3-7
-
MOTOROLA
MC74HC4046A
The output of the VCO is a standard high speed CMOS output with an equivalent LS-TTL fan out of 10. The VCO output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or feed external prescalers (counters) to enable frequency synthesis. Phase Comparators All three phase comparators have two inputs, SIGIN and
VCC SIGIN 14 PC2OUT 13
COMPIN. The SIGIN and COMPIN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard 54HC/74HC input levels are required. Both input structures are shown in Figure 6. The outputs of these comparators are essentially standard 54HC/74HC outputs (comparator 2 is TRI-STATEABLE). In normal operation VCC and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. (The MC14046 also provides a voltage).
VCC
VCC
COMPIN 3
PCPOUT 1 PC3OUT 15 PC1OUT 2
Figure 6. Logic Diagram for Phase Comparators
Phase Comparator 1 This comparator is a simple XOR gate similar to the 54/74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and output waveforms are shown in Figure 7. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range. The capture range for phase detector 1 is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the VCO frequency range. To see how the detector operates, refer to Figure 7. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the
VCO input voltage must increase and the phase difference between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the VCO input is at 0 V. This requires the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is fmax, the VCO input must be VCC and the phase detector inputs must be 180 degrees out of phase.
SIGIN COMPIN PC1OUT VCOIN VCC GND
Figure 7. Typical Waveforms for PLL Using Phase Comparator 1
MOTOROLA
3-8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
The XOR is more susceptible to locking onto harmonics of the SIGIN than the digital phase detector 2. For instance, a signal 2 times the VCO frequency results in the same output duty cycle as a signal equal to the VCO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and VCO range should be designed to prevent locking on to harmonics. Phase Comparator 2 This detector is a digital memory network. It consists of four flip-flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with 0 phase difference between the VCO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that SIGIN is leading the COMPIN. This means that the VCO's frequency must be increased to bring its leading edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the VCO input, increasing the VCO frequency. Once the leading edge of the COMP IN is detected, the output goes TRI-STATE holding the VCO input at the loop filter voltage. If the VCO still lags the SIGIN then the phase detector will again charge up the VCO input for the time between the leading edges of both waveforms. If the VCO leads the SIGIN then when the leading edge of the VCO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the SIGIN is detected at which time the output disables itself again. This has the effect of slowing down the VCO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the VCO will be running either slower or faster than the SIGIN. If it is running slower the phase detector will see more SIGIN rising edges and so the output of the phase comparator will be high a majority of the time, raising the VCO's frequency. Conversely, if the VCO is running faster than the SIGIN, the output of the detector will be low most of the time and the VCO's output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is TRI-STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire VCO frequency range there is no phase difference between the COMPIN and the SIGIN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIGIN is present, the detector will see only VCO leading edges, so the comparator output will stay low, forcing the VCO to fmin. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIGIN, the comparator treats it as another positive edge of the SIGIN and will cause the output to go high until the VCO leading edge is seen, potentially for an entire SIGIN period. This would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. Phase Comparator 3 This is a positive edge-triggered sequential phase detector using an RS flip-flop as shown in Figure 6. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIG IN and COMP IN 's as shown in Figure 9. When the SIGIN leads the COMPIN, the flop is set. This will charge the loop filter and cause the VCO to speed up, bringing the comparator into phase with the SIG IN. The phase angle between SIGIN and COMP IN varies from 0 to 360 and is 180 at fo. The voltage swing for PC3 is greater than for PC2 but consequently has more ripple in the signal to the VCO. When no SIG IN is present the VCO will be forced to fmax as opposed to fmin when PC2 is used. The operating characteristics of all three phase comparators should be compared to the requirements of the system design and the appropriate one should be used.
SIGIN COMPIN PC2OUT HIGH IMPEDANCE OFF-STATE VCOIN PCPOUT VCC GND
Figure 8. Typical Waveforms for PLL Using Phase Comparator 2
SIGIN COMPIN PC3OUT VCOIN
VCC GND
Figure 9. Typical Waveform for PLL Using Phase Comparator 3
High-Speed CMOS Logic Data DL129 -- Rev 6
3-9
MOTOROLA
MC74HC4046A
800 VCC=3.0 V 4.0
VCC=6.0 V VCC=4.5 V VCC=3.0 V
R I = (k )
400 VCC=4.5 V VCC=6.0 V
I I ( A)
0
0 1/2 VCC-1.0 V
1/2 VCC VI (V)
1/2 VCC+1.0 V
-4.0 1/2VCC - 500 mV
1/2 VCC VI (V)
1/2 VCC + 500 mV
Figure 10. Input Resistance at SIGIN, COMPIN with VI = 1.0 V at Self-Bias Point
DEMOD OUT 15 6.0 FREQUENCY STABILITY (%) 10
Figure 11. Input Current at SIGIN, COMPIN with VI = 500 mV at Self-Bias Point
R1=3.0 k R1=100 k 5.0 0 -5.0 -10 R1=3.0 k -15 -100 0 3.0 VCOIN (V) 6.0 -50 R1=100 k R1=300 k R1=300 k
VDEM OUT
VCC=6.0 V RS=300 k VCC=6.0 V RS=50 k VCC=4.5 V RS=300 k VCC=4.5 V RS=50 k VCC=3.0 V RS=300 k VCC=3.0 V RS=50 k 0
VCC = 3.0 V C1 = 100 pF; R2 = ; VVCOIN=1/3 VCC 0 50 100 AMBIENT TEMPERATURE (C) 150
Figure 12. Offset Voltage at Demodulator Output as a Function of VCOIN and RS
Figure 13A. Frequency Stability versus Ambient Temperature: VCC = 3.0 V
15 FREQUENCY STABILITY (%) 10 5.0 0 -5.0 -10 -15 -100
R1=3.0 k FREQUENCY STABILITY (%) R1=300 k R1=100 k
10 8.0 6.0 4.0 2.0 0 -2.0 -4.0 -6.0 -8.0 -10 -100
R1=3.0 k R1=300 k R1=100 k
VCC = 4.5 V C1 = 100 pF; R2 = ; VVCOIN = 1/2 VCC -50 0 50 100 AMBIENT TEMPERATURE (C) 150
VCC = 6.0 V C1 = 100 pF; R2 = ; VVCOIN=1/2 VCC -50 0 50 100 150 AMBIENT TEMPERATURE (C)
Figure 13B. Frequency Stability versus Ambient Temperature: VCC = 4.5 V
Figure 13C. Frequency Stability versus Ambient Temperature: VCC = 6.0 V
MOTOROLA
3-10
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
23 21 19 50 f VCO(MHz) f VCO (KHz) 17 15 13 11 9 7.0 0 0.5 1.0 1.5 2.0 2.5 3.0 VCC = 3.0 V R1 = 3.0 k C1 = 39 pF 3.5 4.0 VCC = 4.5 V 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 VVCOIN (V) R1 = 3.0 k C1 = 0.1 F 3.0 3.5 4.0 VCC = 6.0 V 70 VCC = 4.5 V 60 VCC = 3.0 V
VCC = 6.0 V
VVCOIN (V)
Figure 14A. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
2.0 VCC = 4.5 V VCC = 6.0 V VCC = 3.0 V f VCO(MHz) f VCO (KHz) 1.0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 R1 = 300 k C1 = 39 pF 0 0 0.5 1.0 1.5 2.0 2.5 VVCOIN (V) 3.0 3.5 4.0 4.5 0.2 0.1 0
Figure 14B. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
VCC = 6.0 V VCC = 4.5 V VCC = 3.0 V
R1 = 300 k C1 = 0.1 F 0 0.5 1.0 1.5 2.0 2.5 3.0 VVCOIN (V) 3.5 4.0 4.5
Figure 14C. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
2.0
Figure 14D. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
VCC= 4.5 V C1 = 1.0 F f2 f0 f0 f1
1.0 6.0 V f VCO (%) 3.0 V 0 4.5 V -1.0 6.0 V R2 = ; V = 0.5 V 102 R1 (k) 103
3.0 V -2.0 100
C1 = 39 pF 101
MIN
1/2 VCC
MAX
V = 0.5 V OVER THE VCC RANGE: FOR VCO LINEARITY f0 = (f1 + f2) / 2 LINEARITY = (f0 - f0) / f0) x 100%
Figure 15A. Frequency Linearity versus R1, C1 and VCC
Figure 15B. Definition of VCO Frequency Linearity
High-Speed CMOS Logic Data DL129 -- Rev 6
3-11
MOTOROLA
MC74HC4046A
106
CL = 50 pF; R2 = ; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V; VVCOIN = 1/3 VCC FOR VCC = 3.0 V; Tamb = 25C
106
CL = 50 pF; R1 = ; VVCOIN = 0 V; Tamb = 25C
105 PR1 ( W)
VCC = 6.0 V, C1 = 40 pF VCC = 6.0 V, C1 = 1.0 F
105 PR2 ( W)
VCC = 6.0 V, C1 = 40 pF
104
VCC = 4.5 V, C1 = 40 pF VCC = 4.5 V, C1 = 1.0 F VCC = 3.0 V, C1 = 40 pF
104
VCC = 6.0 V, C1 = 1.0 F VCC = 4.5 V, C1 = 40 pF VCC = 4.5 V, C1 = 1.0 F
103 100 101 R1 (k) 102
VCC = 3.0 V, C1 = 1.0 F
103 100
VCC = 3.0 V, C1 = 1.0 F
VCC = 3.0 V, C1 = 40 pF
103
101
R2 (k)
102
103
Figure 16. Power Dissipation versus R1
Figure 17. Power Dissipation versus R2
103
108
R1 = R2 = ; Tamb = 25C
107 106 (Hz) VCO 105 104 103 102
PDEM ( W)
102
VCC=6.0 V VCC=4.5 V
VCC = 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V
INH = GND; Tamb = 25C; R2 = ; VVCOIN = 1/3 VCC
R1=3.0 k
101
f
VCC=3.0 V
R1=100 k R1=300 k
100 101 102 RS (k) 103
101
102
103 C1 (pF)
104
105
106
Figure 18. DC Power Dissipation of Demodulator versus RS
Figure 19. VCO Center Frequency versus C1
108 107 106 off (Hz) 105 104 103
VCC = 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V
R1 = ; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V; VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25C
108 107 106 105 104 VCC = 4.5 V; R2 =
f
R2=3.0 k
R2=100 k
2 fL (Hz)
R2=300 k
102 101
103 102 10-7 10-6 10-5 10-4 R1C1 10-3 10-2 10-1
101
102
103 C1 (pF)
104
105
106
Figure 20. Frequency Offset versus C1
Figure 21. Typical Frequency Lock Range (2fL) versus R1C1
MOTOROLA
3-12
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
20
R1=3.0 k
14 C1=39 pF
R1=10 k
12 10 FREQ. (MHz) 8.0 6.0 4.0 2.0
R1=3 k R1=10 k R1=20 k R1=30 k R1=40 k R1=50 k R1=100 k R1=300 k
15 FREQ. (MHz)
R1=20 k R1=30 k
10
R1=40 k
R1=50 k
5.0
R1=100 k
C1=39 pF 0 1.0 101 102 R2 ( k)
0
R1=300 k
-2.0 103 104 105
100
101
102
103 R2 ( k)
104
105
106
Figure 22. R2 versus fmax
20 C1=39 pF
Figure 23. R2 versus fmin
2f L (MHz)
R1=10 k R1=3.0 k R1=20 k
10
R1=30 k R1=40 k R1=50 k
R1=100 k R1=300 k
0 1.0 101 102 R2 ( k) 103 104 105
Figure 24. R2 versus Frequency Lock Range (2fL)
High-Speed CMOS Logic Data DL129 -- Rev 6
3-13
MOTOROLA
MC74HC4046A
APPLICATION INFORMATION
The following information is a guide for approximate values of R1, R2, and C1. Figures 19, 20, and 21 should be used as references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC ELECTRICAL CHARACTERISTICS tables.
Phase Comparator 1 R2 = * Given f0 * Use f0 with Figure 19 to determine R1 and C1. (see Figure 23 for characteristics of the VCO operation) R2 Phase Comparator 2 R2 = * Given fmax and f0 * Determine the value of R1 and C1 using Figure 19 and use Figure 21 to obtain 2fL and then use this to calculate fmin. R2 Phase Comparator 3 R2 = * Given fmax and f0 * Determine the value of R1 and C1 using Figure 19 and Figure 21 to obtain 2fL and then use this to calculate fmin. R2
0R
0R
0R
* Given f0 and fL * Calculate fmin fmin = f0-fL * Determine values of C1 and R2 from Figure 20. * Determine R1-C1 from Figure 21. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 21. (see Figure 24 for characteristics of the VCO operation)
* Given f0 and fL * Calculate fmin fmin = f0-fL * Determine values of C1 and R2 from Figure 20. * Determine R1-C1 from Figure 21. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 21. (see Figure 24 for characteristics of the VCO operation)
* Given f0 and fL * Calculate fmin: fmin = f0-fL * Determine values of C1 and R2 from Figure 20. * Determine R1-C1 from Figure 21. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 21. (see Figure 24 for characteristics of the VCO operation)
MOTOROLA
3-14
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4046A
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1 8
-A -
16 9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
3-15
*MC74HC4046A/D*
MC74HC4046A/D MOTOROLA

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